What is RISC-V

RISC, which means reduced instruction set computer, is a microprocessor that executes fewer types of computer instructions.
Risc-v instruction set is an open instruction set architecture (ISA) based on RISC principle. V stands for the fifth generation RISC.
Risc-v (pronounced “risk five”) originated from the University of Berkeley’s student program, and is famous in academia for its open source concept.
The invention team of risc-v founded sifive in 2015, and the risc-v International Foundation was established in the same year.
Sifive aims to promote the commercialization of risc-v. risc-v International Foundation of RISC-V maintains the integrity and non-fragmentation of the instruction architecture

RISC-V History

Distinctive RISC-V


Compare to other commercial ISA, RISC-V ISA is a lot smaller

Design start from zero

Separate usser and privileged isa clearly
Is able to avoid the dependence on micro architecture and technology

Design through community

Designed by academic experts in leading fields and software developers organized community

Free and Open source

Has a lot of open source commercial CPU for users to choose in the market

Highly Extendable and customizable

can be used in all levels of processor cores from microcontrollers to supercomputers can avoid the dependence on micro architecture and technology

growing software ecosystem

There are many open source and commercial tools and operating systems for customers to choose from

Founders of SIFIve

We developed RISC-V

The founders of sifive are professors and Ph.D. of the University of California, Berkeley, who have invented and developed risc-v instruction set architecture (ISA) since 2010.

Risc-v is a free and open isa designed for today’s software stacks. The rapid popularization of the whole industry makes risc-v a new computing standard.